Image Group
Sound Group
Network Group

Image processing group

In general, since data amount processed in image processing systems is quite large, system optimization considering both hardware and software is a key to success. In this research team, aiming at finding novel design method for image processing systems, we are carry on some researches about image processing systems focusing on video coded, video enhancement, and so forth.

Multiple video stream decoding scheme for mobile terminals


Recently we have had many opportunities to watch digital videos on mobile terminals, which include cellular phones and music players, owing to the One-Seg broadcasting service, video sharing websites, Internet television services, and so on. As the number of video contents distributed for mobile terminals has increased, the demand for video search interface to find a desired content quickly has grown. A system where multiple videos displayed on a mobile terminal can be a solution for this demand. On the other hand, some latest HDD and Blu-ray disc recorders can copy recoded videos to mobile terminals, and the display resolution of mobile terminals has become large. In such situation, the demand to watch high resolution videos on mobile terminals has increased. However, computer resources required for simultaneous decoding of multiple videos and decoding of high resolution videos are so considerable that such systems are difficult to realize. Motivated by this, we are researching about the performance optimization of video decoder to realize simultaneous decoding of multiple videos and decoding of high resolution videos on mobile terminals.

Motion-compensated frame interpolation based on feature tracking


Recent advance in the quality of LCDs makes it indispensable to enhance the quality of video sequences. There are two approached for video quality enhancement; one is to increase image spacial resolution, and the other is to increase image temporal resolution, which would be called frame rate. In this research, we are targeting frame rate enhancement by using motion compensated frame interpolation (MCFI). Since many existing MCFI methods are based on matching, it suffers from block noise. In contrast, we are focusing on MCFI based on feature tracking method which is used in object tracking field. The proposed method estimates motion vectors from tracked features, and interpolates the frame by pixel-by-pixel scheme. By using our method, high quality block-noise free video sequences can be generated.

A study on real-time Retinex video image enhancement


Recently, consumer digital imaging devices such as digital cameras and color liquid crystal displays have been gaining much popularity. Digital image enhancement in terms of color tone and/or contrast is indispensable for these kinds of consumer imaging devices. General image enhancement schemes, such as gamma correction and histogram equalization, are used for long years, which compensate each pixel value uniformly based on given equations or look-up tables. In contrast, adaptive image enhancement schemes may refer surrounding pixels to reproduce a high quality image. However, existing adaptive image enhancement schemes suffer from high computational cost, and therefore effective reduction of the computational cost is required for practical application. Motivated by this, in this research topic, we are developing an efficient real-time Retinex video image enhancement scheme, which includes hardware implementation. Currently, we focus on the Retinex theory and its quadratic programming (QP) model.

An image compression method for frame memory reduction


Recently, large sized plasma or LCD TV sets are gaining popularity, since high-definition video appeared such as digital terrestrial television and Blu-ray Disc. In these visual devices, a large frame memory is required, and large power is dissipated due to data transfer, because of increase of the data size. Motivated by this, we research about the method to reduce the size of the frame memory to install compresses and decompresses between an image processing part and a frame memory.

An efficient hardware architecture for adaptive deinterlacing


Interlaced video sequences are widely used for digital terrestrial television and camcorders. However, it cannot be be displayed accurately on LCDs, which display video sequences by progressive scanning. Therefore, it is necessary to convert video sequences from interlaced format to progressive format. This conversion is called deinterlacing, it is implemented as LSIs and processed at real-time in LCD TVs. Various deinterlacing methods has been researched, because it influences the quality of video so much. Methods based on motion compensation can achieve high-quality deinterlacing. However, they require much computational cost in terms of processing time and hardware resources. Motivated by this, we are researching about an efficient hardware architecture for deinterlacing to relief the computational cost, keeping its conversion quality high.

A study on noise evaluation scheme for consumer camcorders


Various kinds of noise are included in video sequences recorded by consumer camcorders. In addition, recent advance in camcorders in terms of its integration, such as sophisticated functionalities by signal processing with compact body, has made it impossible to separate each noise from the resulted video sequence. In order to evaluated noise during its development, video quality experts evaluate the video quality subjectively using prototype camcorders. This evaluation scheme requires much cost in terms of man-hours, and limits the turn around time of the development of camcorders. Motivated by this, we are researching about an efficient noise evaluation scheme and its implementation in terms of noise evaluation systems.

Sound Group

We are carrying on some researches about sound/speech processing for embedded platforms. Our works involve fundamental research and practical implementation for 3D sound effect, some voice technologies, and so on.

3D Sound Effects for Embedded Systems


A certain sound is influenced by the surrounding environment such as diffraction and reflection. Subsequently, the sound arrives at the both eardrums of the listener's ears, and then the listener perceives the sound by an auditory organ. The spatial image perceived by human auditory sense in such a way is referred to as a "sound image," and perception of direction and distance of a sound image is referred to as "sound localization."

If the factors of sound localization are explicated and can be controlled by digital signal processing, a listener can experience the virtual sound to the same degree as experiencing the actual sound in the real world. Our group is researching the method to simulate transfer functions from a sound source to a listener at low computational cost. Our method can reduce computational cost based on feature extraction of the functions so that real-time implementation in embedded platforms is applicable.

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Direction of Arrival Estimation of Speech using Microphone Array


There are numerous examples of applications currently incorporating peech direction of arrival (DOA) estimation of human speech, such as video conferencing, sound recording enhancement, speech recognition and recently interactive robots.

Current DOA estimation systems have to deal with the unavoidable trade-off between accuracy and system size. In other words, to achieve higher accuracy, the number of elements needs to be increased and with that array size. However, large size arrays have a number of issues preventing it from being used by small, low cost applications. We are considering highly accurate DOA estimation systems for speech with two channel microphone array, based on non-utterance frame omission and fundamental frequency selection.

Speech Recognition for Embedded Systems


Speech recognition technology is expected to provide more convenient and natural interface than existing input devices such as key-board, ten-key pad, and so on. Although continuous speech recognition allows a user to speak without pauses among words, the process incurs high computation load and thus it is difficult to realize practical recognition system on embedded platform.

Motivated by this technical issue, we are devising an efficient pipeline technique of continuous speech recognition for embedded system implementation. In our work, a continuous speech recognition system Julius is employed and an ARM is used as the embedded processor.

VLSI Design and CAD Group

This group researches VLSI design methodology, circuit technology and architecture for future advanced integrated devices. Focusing on timing, power dissipation and reliability that determines chip performance and quality, we are studying system integration, VLSI chip design and CAD algorithms.

VLSI Self Performance Compensation


VLSIs are facing a crucial obstacle that prevents future performance improvement, that is manufacturing variability and environmental fluctuation (supply voltage and temperature) are significantly increasing and affecting VLSI performance. In addition, circuit aging is also becoming a critical design issue for performance variation. This research aims to establish a circuit and design methodology for realizing VLSIs that compensate their performance automatically based on sensed variability and aging information. We are also validating the methodology with chip fabrication and measurement. 

Subthreshold Circuit Design for Ultra Low Power Applications

Sensor network is drawing a lot of attention as a technology for realizing future secure and safe society. Sensor nodes, which compose a sensor network, are required to operate for a long time with power supply whose capacity is limited, such as button and solar cells, and hence ultra low power design is highly demanded. Recently, for such a purpose, subthreshold circuits are proposed. Subthreshold circuit operates at very low supply voltage, and it consumes extremely small power though its speed is very slow. On the other hand, the characteristics of subthreshold circuits are much different from those of normal superthreshold circuits. Therefore new circuit techniques and design methodology are necessary. We are studying for establishing a design methodology tailored for subthreshold circuits and designing VLSI chips for the design methodology validation.

On-chip Small True Random Number Generator


As social infrastructure is constructed on ICT, information security, especially importance of random number is increasing. For encryption, true random number, which has unpredictability and is generated exploiting physical statistical fluctuation, is demanded. However, pseudo random number generators are used instead of true random number generator, and the predictability of random number has not sufficiently assured. This research aims to develop an on-chip small true random number generator, and provides an environment that true random number with unpredictability is easily used for key generation and encryption. We focus on oscillator-based true random number generator that is robust to external perturbation (noise from other circuits and side-channel attack), and study self-tuning of circuit operation to cope with manufacturing and environmental variability and assure quality of random number.

Timing Design Methodology for Nano-scale Generation


In nano-scale VLSIs, manufacturing variability and power supply noise significantly fluctuate circuit performance. To achieve high-speed operation and attain high reliability, a new design methodology is necessary. We are researching measurement, verification, prediction and suppression techniques for power supply noise, and mitigation techniques for manufacturing variability. For noise measurement and validation of noise suppression, we design and measure VLSI chips.

Static timing analysis with a unified approach to manufacturing and environmental variability


VLSI fabrication necessarily involves manufacturing variability. In addition, in actual operating condition, power supply voltage and temperature fluctuate. In current advanced technologies, the impact of these variabilities on circuit performance is significantly increasing, and its estimation before fabrication is getting difficult. This research is developing a timing analysis method that aims at taking both static manufacturing variability and dynamic environmental fluctuation into consideration simultaneously. To realize this, we have developed a gate delay model for large variability and statistical modeling of power supply noise.

Network Group

With the recent rapid development of smart appliances, home networking technology becomes to attract public attention. This group researches on home network platform.

Home Networking Platform

The home network is built easily with wireless communication standard, such as IEEE802.11 or IEEE802.15.4, which utilizes ISM band. However the throughput becomes low since a channel in ISM band is shared with many nodes by using Carrier Sense Multiple Access/Collision Avoidance (CSMA/CA).

Cognitive radio is a very promising technique to solve such a problem. In such a cognitive radio system, each wireless node changes transmission parameters according to communication environment surrounding the node.

We are studying about home network platform which has the capability of both "environment cognition" such as location estimation of wireless nodes or carrier sensing and "adaptive operation" such as dynamic selection of spectra according to result of environment cognition.


Dependable VLSI Group

Scaling of integrated circuits has enabled electronics to merge with almost all fields, which in turn offers man kind evermore convenient products and systems dedicated for the ease of life and luxury. Unfortunately, process scaling is accompanied with numerous undesirable phenomenons such as, circuit degradation, sensitivity to radiation, current leakage and so on. Such phenomenons require designers to provide special attention, and also offer opposing solutions. In this research group, students are given the chance to face challenges similar to the ones encountered by designers dealing with cutting edge technologies, to study, design and implement circuits that have the ability to perform unlimited tasks upon reconfiguration, to investigate radiation effect and techniques to mitigate it, and to design and implement mechanisms that grant circuits the ability to heal itself to mitigate degradation and provide a long lasting lifespan.

FRRAry : Flexible Reliability Reconfigurable Array


In this research, we develop circuits (reconfigurable logic) which can change their function according to bit streams of data referred to as configuration information. Upon setting different configuration information, the logic can be reconfigured to perform unlimited tasks. When thinking about reconfigurable architecture design, it is necessary to take into account diversity of functionality, flexibility of interconnect, performance and power consumption, and reliability considerations. Here, we get introduced to the world of fine-grained and coarse-grained reconfigurable architectures, and also, we have the chance to be an active part of the reconfigurable architecture design process leveraging the four considerations mentioned above. Moreover, through out the course of this research, students gain essential hands-on experience in the hardware development process involving design, implementation, pre-silicon verification, layout, post-silicon verification and validation.

Degradation Effects of Circuit


In recent years, degradation effects of circuit such as HCI (Hot Cariier Injection), TDDB (Time Dependence Dielectric Breakdown), NBTI (Negative Bias Temperature Instability) become a more considerable issue. In these effects, NBTI is one of serious aging problem, increasing threshold voltage and leading a timing degradation. NBTI effect has two phases, stress and recovery. Stress means PMOS is active, in other words, gate voltage is negatively biased. In this phase, Vth increases gradually. On the other hand, in recovery phase, which means PMOS is OFF, Vth gradually decreases to its initial value before stress undergoing. In this work, we research and recognize these degradation effects. Moreover, we consider architectures which enable to mitigate circuit delay degradation.

SET Pulse Width Measurement Circuit


As VLSI technology advances, soft error is becoming a serious issue in digital circuit design. Soft error arises when radiation particles collide with Si substrate and electrons/holes charge are induced and collected. When an SET (Single Event Transient), which is a kind of soft error generated in a combinational circuit, propagates to a sequential element and is captured at clock edges, the SET pulse causes an error. Information on the distribution of SET pulse width is eagerly demanded for SET-oriented soft error estimation and suppression because a wider SET pulse more probably causes an error. On the other hand, existing SET pulse width measurement circuits have remaining issues to resolve for obtaining the distribution. This research aims to develop SET pulse width measurement circuit to satisfy the requirements suitable for precise SET pulse width measurement.

Last-modified: 2010-04-07 (Wed) 15:08:22